1. Field of the Invention
The invention relates to electronic xe2x80x9csample and holdxe2x80x9d circuits (alternately referred to as xe2x80x9ctrack and holdxe2x80x9d, xe2x80x9csamplerxe2x80x9d circuits or xe2x80x9csub-sampling mixersxe2x80x9d) and, in particular to such circuits which may implemented in integrated form (i.e. integrated semiconductor circuits).
2. Description of the Related Prior Art
Sampling circuits, using sampling gates, are commonly used in a variety of circuit applications to sample and hold analog signals for further processing. For example, such circuits are used in analog-to-digital converters, switch capacitor filters and other sampled domain circuits. The use of analog-to-digital converters (ADC""s) in mixed signal integrated circuit systems is common and the function and design of many ADC circuits is known to persons skilled in the art. Generally, they function to convert an analog signal into a digital representation and include sample-and-hold circuits (also referred to herein, more simply, as sampling circuits).
Typically, a sampling circuit at the front end of an ADC circuit samples the input analog signal using appropriately configured sampling gates. This analog signal sampling step is referred to as the xe2x80x9csamplingxe2x80x9d (or xe2x80x9ctrackingxe2x80x9d) mode of the operation of a sampling circuit. The sampling circuit operates on a cyclical basis at a predetermined sampling (clock) frequency.
Two main modes of operation are associated with sampling circuits, namely, the aforementioned sampling mode and the xe2x80x9choldxe2x80x9d mode. In the sampling mode of operation the sampling circuit allows the input signal to propagate through the sampling gates to one or more capacitors, also referred to as xe2x80x9choldxe2x80x9d capacitor(s), where it is stored (i.e. maintained) until the end of a predetermined sampling time period when another sampling operation takes place and a new sampled signal arrives at the capacitor and is stored. During the hold mode of operation the objective is to block the input signal from propagating through the sampling gates and isolate the signal stored by the hold capacitor(s) so that it remains essentially unchanged and unaffected by any change of the input signal during the governing hold mode time period.
Many specific sampling circuits are known in the art. Examples of these are described in the following patent references: U.S. Pat. No. 4,962,325 issued Oct. 9, 1990, U.S. Pat. No. 5,315,170 issued May 25, 1994, U.S. Pat. No. 5,389,929 issued Feb. 14, 1995, U.S. Pat. No. 6,028,459 issued Feb. 22, 2000, U.S. Pat. No. 6,262,277 issued Jul. 17, 2001, U.S. Pat. No. 6,275,076 issued Aug. 14, 2001 and U.S. Pat. No. 6,384,758 issued May 7, 2002.
However, the known sample and hold circuits have not been successful to efficiently and effectively establish isolation between the input signal and the hold capacitor(s) during the hold mode and the degree to which effective isolation can be achieved is often a limiting factor in the performance and usefulness of these circuits. This is due to the occurrence of signal leakage during the hold mode of operation permitted by parasitic components inherent to the sampling gates, whereby undesired parts of the input signal are able to pass through to the hold capacitor(s). These parasitic components represent a low impedance between the inputs and hold capacitor(s).
Radio frequency (RF) or intermediate frequency (IF) sampling circuits are sometimes referred to as sub-sampling mixers because the act of sampling a high frequency signal with a lower frequency sampling clock has the effect of both sampling the signal and mixing the frequency down, as understood by one skilled in the art. The parasitic components of the sampling circuit present a particularly difficult problem for sampling gates used for RF and IF sampling circuits in wireless receivers.
By reason of the foregoing limitations of known sampling circuits, there exists a need for new and effective means to improve the isolation level achievable by such circuits during the hold mode of their operation.
In order to overcome the deficiencies of the prior art, the present invention provides a new and effective means for achieving improved isolation in a sampling circuit during the hold mode of its operation. It has been discovered that that an effective isolation can been achieved during the hold mode of operation of a sampling circuit by providing parallel circuit paths, which are identical (electronically equivalent) and therefore provide the same impedance leading to the hold capacitor(s), and applying differential inputs in a configuration which cancels (subtracts) any feed through (leakage) input signal to the storage means during the hold mode of operation. This approach contrasts with the conventional approaches typically taken for the design of sampling circuits which focus on the parasitic characteristics or effects of the individual circuit elements.
In accordance with one aspect of the invention there is provided a sampling circuit configured for operating in a sampling mode and a hold mode on an alternating basis at a predetermined sampling frequency, the sampling circuit comprising: a primary sampling signal path comprising sampling means configured for sampling a differential input signal (Vin+, Vinxe2x88x92) and transmitting a sampled signal corresponding to the differential input signal for storage by storage means, during the sampling mode of operation of the sampling circuit, and for blocking the input signal from the storage means during a hold mode of operation of the circuit; and, an isolation signal path in parallel with the primary sampling signal path and comprising means for blocking the differential input signal from said storage means during the sampling and hold modes of operation of the sampling circuit, wherein the sampling and blocking means are configured to present substantially the same impedance to the differential input signal and to effectively cancel, during the hold mode of operation, any leakage of the differential input signal transmitted through the primary and isolation paths.
In accordance with a second aspect of the invention there is provided a method for sampling a signal comprising the steps: providing a differential signal (Vin+, Vinxe2x88x92); sampling the differential signal and transmitting a sampled signal corresponding to the differential signal through a primary sampling signal path for storage by storage means, during a sampling period, and blocking the differential signal from said storage means during a hold period, whereby the sampling and hold periods alternate at a predetermined sampling frequency; providing an isolation signal path in parallel with the primary sampling signal path and blocking the differential signal from the storage means during the sampling and hold periods, whereby the primary sampling signal and isolation signal paths present substantially the same impedance to the differential input signal; and configuring the differential signal relative to the primary sampling and isolation signal paths such that, during the hold period, any leakage of the differential signal transmitted through the primary sampling and isolation signal paths is cancelled.
Accordingly, the present invention advantageously provides an environment in which differing levels of leakage input signal components, to the storage means, can be tolerated and, in fact, used to cancel them out before they are xe2x80x9cseenxe2x80x9d by the storage means or produce any detrimental effect on the sampling functionality of the circuit.